FIG. 1 illustrates a conventional memory cell in a Dynamic Random Access Memory (DRAM). The memory cell includes a transistor M1 and a cell capacitor connected in series between a bit line and a voltage VP. A gate of the transistor M1 is connected to a word line. The refresh time of the DRAM memory cell is decreased by two major types of leakage current: I1 which is junction leakage current caused by defects at the junction boundary of transistor M1; and I2 which is channel leakage current caused by sub-threshold current flowing through the transistor M1.
The junction leakage current I1 can be reduced by decreasing the channel implantation dose, but this can cause I2 to increase. Similarly, the sub-threshold current I2 can be reduced by increasing the threshold voltage Vth of M1, but this can cause I1 to increase.
A negatively biased word line scheme has been devised to reduce both junction leakage current and channel leakage current at the same time. A memory device employing a negative word line scheme applies a negative voltage VBB (typically −0.4 to −0.5 Volts) to the word lines of non-selected memory cells.
The memory devices employing negatively biased word line schemes, however, can be subject to noise problems. Noise can be generated by the influx of discharge current into a negative voltage source. That is, the influx of discharge current into the negative voltage source occurs when a word line is discharged from a boosting voltage or supply voltage to a negative voltage during a precharge operation. When these discharge currents are excessively high, noise occurring in the negative voltage VBB increases and may cause the semiconductor memory device to operate erroneously.